- Product :
- Minimum Operating Temperature :
- Maximum Operating Temperature :
- Number of Logic Array Blocks - LABs :
- Operating Supply Voltage :
- Number of Logic Elements :
0 products
IMAGE | PART NO. | PRICE | QUANTITY | STOCK | MANUFACTURE | DESCRIPTION | Product | Mounting Style | Package / Case | Minimum Operating Temperature | Maximum Operating Temperature | Packaging | Number of Logic Array Blocks - LABs | Number of I/Os | Operating Supply Voltage | Number of Logic Elements | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix IV E 32522 L... | Mechanical Life | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Power Supply Rejection Ratio (PSRR) | Harmonized Tariff Schedule (HTS) Code | 900 mV | ion Loss (dB) | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix IV E 32522 L... | Mechanical Life | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Power Supply Rejection Ratio (PSRR) | Harmonized Tariff Schedule (HTS) Code | 900 mV | ion Loss (dB) | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix IV E 32522 L... | Mechanical Life | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Power Supply Rejection Ratio (PSRR) | Harmonized Tariff Schedule (HTS) Code | 900 mV | ion Loss (dB) | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix IV E 32522 L... | Mechanical Life | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Power Supply Rejection Ratio (PSRR) | Harmonized Tariff Schedule (HTS) Code | 900 mV | ion Loss (dB) | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix IV E 32522 L... | Mechanical Life | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Power Supply Rejection Ratio (PSRR) | Harmonized Tariff Schedule (HTS) Code | 900 mV | ion Loss (dB) | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix IV E 32522 L... | Mechanical Life | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Power Supply Rejection Ratio (PSRR) | Harmonized Tariff Schedule (HTS) Code | 900 mV | ion Loss (dB) | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix IV E 32522 L... | Mechanical Life | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Power Supply Rejection Ratio (PSRR) | Harmonized Tariff Schedule (HTS) Code | 900 mV | ion Loss (dB) | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | 0 C | + 70 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix IV E 32522 L... | Mechanical Life | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Power Supply Rejection Ratio (PSRR) | Harmonized Tariff Schedule (HTS) Code | 900 mV | ion Loss (dB) | |||||
|
Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 13500 L... | Stratix III | SMD/SMT | Switching Current | - 40 C | + 85 C | Tray | Core Architecture | Harmonized Tariff Schedule (HTS) Code | 1.2 V to 3.3 V | Load Impedance |